![]() ![]() The testbench instantiates our circuit as dut at line 69. In order to simulate a benchmark we need a test bench which will stimulate our circuit (the Device-Under-Test or DUT).Īn example test bench which will randomly perturb the inputs is shown below:ġ `timescale 1 ps / 1 ps 2 module tb () 3 4 localparam CLOCK_PERIOD = 8000 5 localparam CLOCK_DELAY = CLOCK_PERIOD / 2 6 7 //Simulation clock 8 logic sim_clk 9 10 //DUT inputs 11 logic \top^tm3_clk_v0 12 logic \top^tm3_clk_v2 13 logic \top^tm3_vidin_llc 14 logic \top^tm3_vidin_vs 15 logic \top^tm3_vidin_href 16 logic \top^tm3_vidin_cref 17 logic \top^tm3_vidin_rts0 18 logic \top^tm3_vidin_vpo~0 19 logic \top^tm3_vidin_vpo~1 20 logic \top^tm3_vidin_vpo~2 21 logic \top^tm3_vidin_vpo~3 22 logic \top^tm3_vidin_vpo~4 23 logic \top^tm3_vidin_vpo~5 24 logic \top^tm3_vidin_vpo~6 25 logic \top^tm3_vidin_vpo~7 26 logic \top^tm3_vidin_vpo~8 27 logic \top^tm3_vidin_vpo~9 28 logic \top^tm3_vidin_vpo~10 29 logic \top^tm3_vidin_vpo~11 30 logic \top^tm3_vidin_vpo~12 31 logic \top^tm3_vidin_vpo~13 32 logic \top^tm3_vidin_vpo~14 33 logic \top^tm3_vidin_vpo~15 34 35 //DUT outputs 36 logic \top^tm3_vidin_sda 37 logic \top^tm3_vidin_scl 38 logic \top^vidin_new_data 39 logic \top^vidin_rgb_reg~0 40 logic \top^vidin_rgb_reg~1 41 logic \top^vidin_rgb_reg~2 42 logic \top^vidin_rgb_reg~3 43 logic \top^vidin_rgb_reg~4 44 logic \top^vidin_rgb_reg~5 45 logic \top^vidin_rgb_reg~6 46 logic \top^vidin_rgb_reg~7 47 logic \top^vidin_addr_reg~0 48 logic \top^vidin_addr_reg~1 49 logic \top^vidin_addr_reg~2 50 logic \top^vidin_addr_reg~3 51 logic \top^vidin_addr_reg~4 52 logic \top^vidin_addr_reg~5 53 logic \top^vidin_addr_reg~6 54 logic \top^vidin_addr_reg~7 55 logic \top^vidin_addr_reg~8 56 logic \top^vidin_addr_reg~9 57 logic \top^vidin_addr_reg~10 58 logic \top^vidin_addr_reg~11 59 logic \top^vidin_addr_reg~12 60 logic \top^vidin_addr_reg~13 61 logic \top^vidin_addr_reg~14 62 logic \top^vidin_addr_reg~15 63 logic \top^vidin_addr_reg~16 64 logic \top^vidin_addr_reg~17 65 logic \top^vidin_addr_reg~18 66 67 68 //Instantiate the dut 69 sv_chip3_hierarchy_no_mem dut (. ![]() The DFF latch_top\^FF_NODE\~387 has a clock-to-q delay of 124 ps and a setup time of 66ps. In this case the routing segment routing_segment_lut_n616_output_0_0_to_lut_n497_input_0_4 has a delay of 312.648 ps, while the LUT lut_n452 has a delay of 261 ps from each input to the output. Here we see the timing description of the cells in Listing 19. ![]() ![]() The SDF defines all the delays in the circuit using the delays calculated by VPR’s STA engine from the architecture file we provided. ![]()
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